(1) Technical Field
This disclosure relates generally to DC-to-DC converters and relates more specifically to linear regulators as e.g. low-dropout (LDO) regulators having an output transistor leakage current compensation.
(2) Description of the Prior Art
A low-dropout or LDO regulator is a DC linear voltage regulator, which can operate with a very small input-output differential voltage. The advantages of a low dropout voltage regulator include a lower minimum operating voltage, higher efficiency operation and lower heat dissipation. The main components of a LDO are an output power transistor (FET or bipolar transistor) and a differential amplifier (error amplifier). One input of the differential amplifier monitors the fraction of the output determined by a feedback voltage divider having a divider ratio. The second input to the differential amplifier is from a stable voltage reference (bandgap reference). If the output voltage rises too high relative to the reference voltage, the drive to the output power transistor changes to maintain a constant output voltage.
Usual LDO applications require source capability by using one output transistor only and therefore do have the usual LDO implementation a sourcing output transistor stage only. Any topology with sink-and-source capability will require a second output transistor and hence more silicon area and furthermore a corresponding control circuitry which will increase also the quiescent current consumption. The sink capability of a LDO with source transistor output stage is limited by its internal circuit current consumption. Especially for very low-power LDOs or low-power mode of LDO the current consumption of the internal circuitry is in the range of a few-uA or even far below 1 uA. Therefore is nearly no sink capability available.
If the LDO is operated at higher temperature, i.e. above 125 degrees Celsius, the leakage current of a big output transistor gets relevant and could exceed the sink capability. The result would be an increase of LDO output voltage, which could in worst-case jump up to the LDO input voltage and the regulation capability of the LDO will be completely lost.
In order to overcome this problem a voltage monitor and clamping circuitry could be used. The drawback of this solution is an additional current consumption by such circuitry, which is not really acceptable for ultra low-power designs. Another solution could be a LDO with source-sink output stage as mentioned above. Again, such output stage requires more complex control and hence have drawback on maintaining the loop stability for the whole circuitry and furthermore will cause additional current consumption as well.
A very simple solution could be to add a constant-current sink with a fix value of the maximum expected leakage current of the source output transistor. But this would again clearly increase the current consumption, even at room temperature.
It is a challenge for engineers designing LDOs to compensate leakage current efficiently, i.e. without additional power consumption or without complex control.